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Jan. 25, 1966 E. B. wlLENlTz 3,231,865

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iii! 1|||||L INVENTOR. Evelyn Berezin Wiiem'z Figli am, a1 7M Maf/T .IPNEYS United States Patent O 3,231,865 ON-LINE DATA TRANSFER APPARATUS Evelyn Berezin Wilenitz, New York, N.Y., assignor to The Bunker-Ramo Corporation, a corporation of Delaware Filed July 7, 1961, Ser. No. 122,491 28 Claims. (Cl. S40-172.5)

termed the peripheral equipment. The peripheral equipment can include, for example, magnetic drums, magnetic tapes, automatic typewriters, teletype units, punched card equipment, paper tape punches, and readers. Also included are specially designed input/output devices called keysets, as well as the logical circuitry operating to effect transfer of information to or from the processor.

This invention is especially directed to so-called online systems, i.e. systems required to receive information on a random basis from many sources, sometimes over great distances, and to process this information and send e back answers, all in very short time periods. On-line data processing systems have been used for many years for industrial and military problems which may broadly be termed inventory control, and which may be regional, nationwide or even worldwide in scope. Examples of such problems are the control and reservation of passenger or cargo space in the transportation industry; the handling of deposits and Withdrawals in a savings bank with many branches; the processing, distributing and retrieval of information concerning stock transactions and quotations; and the control of product or supply inventory for large scale manufacturing and distributing organizations.

Computers designed for on-line data processing Work have unique requirements not present in the usual cornmercial data processing situations. Among these requirements are the need for highly reliable continuous performance, multiple inputs, very large storage of information,

ability to handle peak loads without Waste of computer r power, and ability to quickly change programs from one type of transaction to another.

Fast access to large amounts of information, combined with high speed processing of that information, is best achieved by performing the arithmetic (processor) operations in parallel with information transfer to or from the peripheral equipment. In other Words, computation is performed in the central processor concurrently with the transfer of data to or from the many different storage devices or input-output devices of the peripheral equipment. Since the central processor normally operates much faster than the terminal equipment, this simultaneous computation and information retrieval assures that full advantage is taken of the processor speed, i.e. the processor need not be required to operate at the slower speed of the peripheral equipment.

In the illustrative embodiment of the present invention to be described herein, the system is so arranged that data required from the peripheral equipment is transferred almost immediately to the central processor, one digit at a time. This is accomplished by an interlacing system of data transfer in which the processor is stopped 3,231,865 Patented Jan. 25, 1966 whenever a digit of the data is available for transfer to the processor. This result is achieved by means of peripheral equipment control registers which, once activated by the central processor, independently control the transfer of data between the peripheral unit and the processor.

Since each digit as it becomes available is almost immediately transferred to the processor, this system does not require large and costly buffer registers for each peripheral unit. A small (e.g. four character) synchronizing register is all that will normally be required. Still another advantage of such a system is that processing can commence immediately when the first character is available and transferred to the processor.

Since with this system many peripheral units may be in condition to transfer data to or from the processor core memory at the same time, and because with such a core memory only one address can be selected during any one core cycle, a predetermined set of transfer priorities are provided to control the data transfer. For example, a magnetic tape unit is given higher priority than a magnetic drum, since if a tape character is missed it is necessary to go through the rather lengthy procedure of stopping and rewinding the tape, and then making another pass in the forward direction, whereas if a drum character is missed it can be picked up automatically on the next drum spin.

A priority selector circuit, to be described hereinbelow in detail, receives BD" signals from the various peripheral equipments indicating that information transfers are to be made, selects a particular peripheral equipment according to a preset priority schedule, and develops an allow" signal indicating the peripheral equipment selected for transfer of data to or from the processor core memory. If a magnetic tape unit, for example, is assigned top priority', and is in condition to place a digit in the processor core memory at the same instant that a magnetic drum assigned the next priority also is so conditioned, the transfer from the drum will be delayed until the tape digit transfer is complete.

Peripheral equipment control registers are provided to control the transfer of data between peripheral equipments and the processor core memory. Typically, these control registers contain information defining the function to be executed (for example, read or write), the processor core location to or from which data is to be transferred, and the location in the peripheral equipment to or from which data is to be transferred. Thus the peripheral equipment can, for short periods of time, be operated by the control register independently of the central processor. When a control register has been fed a transfer instruction, that register assumes complete control of the actual data transfer, and the peripheral equipment is, in effect, disconnected from the central processor to carry out the instruction independently of the processor or any other peripheral equipments. In other words, the peripheral equipments take key instructions from the processor and sequence through a limited series of steps under their own control.

Once the transfer instruction has been fed to the peripheral equipment control register the processor is free to carry out other instructions in accordance with its own internal program. The peripheral equipment will be operating simultaneously and, when it requires access to the processor core memory, it indicates this by a signal on its BID circuit. The priority selector circuit receives this signal, selects a particular peripheral equipment if more than one is bidding simultaneously, and activates an interrupt circuit which stops the processor for a sutlicient time for the required data to be transferred to or from the core memory. This priority-interrupt feature thus allows any peripheral equipment, while sequencing 

1. AN ON-LINE DATA PROCESSING SYSTEM FOR PROCESSING CALL REQUESTS FROM KEYSETS AND THE LIKE COMPRISING A CENTRAL PROCESSING PORTION, SAID CENTRAL PROCESSING PORTION INCLUDING COMPUTER MEANS AND MEANS FOR RECEIVING SAID CALL REQUESTS, A PLURALITY OF PERIPHERAL UNITS, EACH OF SAID PERIPHERAL UNITS INCLUDING INFORMATION STORAGE MEANS AND CONTROL REGISTER MEANS, SAID CONTROL PROCESSING PORTION ALSO INCLUDING MEANS RESPONSIVE TO A RECEIVLED CALL REQUEST FOR DIRECTING TO SAID CONTROL REGISTER MEANS DATA FOR CONTROLLING THE TRANSFER OF INFORMATION BETWEEN SAID INFORMATION STORAGE MEANS AND SAID CENTRAL PROCESSING PORTION, AND TRANSFER MEANS FOR EACH OF SAID PERIPHERAL UNITS, SAID TRANSFER MEANS BEING CONTROLLED BY SAID CONTROL DATA TO CARRY OUT THE TRANSFER OF INFORMATION BETWEEN THE CORRESPONDING ONE OF SAID PERIPHERAL UNITS AND SAID CENTRAL PROCESSING PORTION. 